USB 2.0 PHY
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  3. 接口IP
Highlights
  • Designed for TSMC 22nm/55nm/110nm process node
  • Supports HighSpeed 480Mbps data rate and is backward compatible with USB1.1 data rates
  • Interges high-speed and mixed-signal circuitry designed to UTMI+ specifications
  • Can be used in USB Device, Hub and Host applications
  • Designed for easy integration with GL USB2.0 building blocks/ controllers
Target applications Techonology
  • TSMC 22nm/55nm/110nm process
Overview
The GL USB2.0 PHY IP provide designers with a complete physical (PHY) layer IP solution for consumer applications such as digital cameras, edge devices, media players and other consumer electronics requiring high-throughput USB capabilities. The GL USB2.0 PHY IP offers a small die size with low power consumption.
Architected for the industry’s most advanced 1.0V process technologies, the GL USB2.0 PHY IP are designed with features created to minimize effects due to variations in foundry process, device models, packages, and board parasitics. The GL USB2.0 PHY IP build on years of customer success with GL’s silicon-proven GL USB2.0 product line, which has been ported to many process nodes. When combined with GL digital controllers, the GL USB2.0 PHY IP provides a complete solution for low-power, small die area needs in advanced system-on-chip (SoC) designs.
 

                                                                                        
Key Features
  • Integrated includes transmitter, receiver, regulator, PLL, digital core, and ESD I/O pads in PHY hard macro
  • Built-In Self-Test (BIST) features for efficient production testing and debug capabilities
USB 2.0 Features
  • 480 Mbps High-Speed and 12 Mbps Full-Speed data rate
  • UTMI+ interfaces
  • Supports suspend, resume, and remote wakeup

 
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