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2026-07-27
GenesysLogic Showcases In-House USB4 PHY IP, Expanding Its High-Speed SerDes IP Portfolio
In the second quarter of 2026, GenesysLogic showcased its in-house USB4 PHY IP through technical demonstrations with multiple customers, highlighting the company’s continued advancement in high-speed PHY and SerDes technologies.
The demonstrated USB4 PHY IP complies with the USB-IF USB4 V1.0 specification and supports data rates of up to 40Gbps. Designed with excellent signal integrity, low power consumption, and broad protocol compatibility, it is well suited for high-speed applications including PCs, AI computing, high-performance computing (HPC), and data center connectivity.
In addition, GenesysLogic’s USB 3.2 Gen2 PHY IP has been validated in multiple customer projects and is already in mass production, delivering reliable 10Gbps performance. Together, the USB4 PHY and USB 3.2 Gen2 PHY form a comprehensive high-speed PHY IP portfolio to address a wide range of application requirements.
Beyond IP licensing, GenesysLogic also provides porting, system integration, validation, and production support services to help customers accelerate SoC development and shorten time-to-market.
Looking ahead, GenesysLogic will continue to expand its high-speed PHY and SerDes IP portfolio across multiple process nodes and foundries, delivering reliable and scalable interface IP solutions for the global semiconductor industry.
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