MIPI D-PHY (RX)
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Highlights
  • Complete MIPI D-PHY v1.0 Receiver Solution
  • Includes Analog PHY and Digital CIL Controller
  • Supports up to 4 Data Lanes and 1 Clock Lane
  • High-Speed (HS) and Low-Power (LP) Reception
  • Protocol Layer Features: ECC, CRC, Frame/Line Decoding
  • Direct DVP Output Interface for Display or ISP
Target applications
  • Mobile Image Sensors and Camera Interfaces
  • Display Input Modules
  • SoC Multimedia Subsystems
Overview
The MIPI RX Controller IP is a fully integrated solution that consists of a MIPI-compliant analog D-PHY receiver and a digital CIL (Clock and Interface Logic) controller. The analog PHY handles the differential signaling and low-power transitions per MIPI D-PHY v1.0 standard, while the digital CIL processes protocol-level decoding, error checking, and video stream interfacing. It supports up to four data lanes and one clock lane for high-throughput unidirectional data reception.
Designed for seamless integration into SoCs, the controller interfaces with APB registers, provides programmable power management, supports ECC/CRC checking, and outputs video data through a parallel DVP interface. Internal modular interfaces also expose rich diagnostic and calibration hooks for robust bring-up and debug.
 
Key Features
  • MIPI D-PHY v1.0 compliant
  • Unidirectional analog PHY with integrated CIL
  • Supports 1 to 4 data lanes and 1 clock lane
  • High-Speed mode: 80 Mbps to 1.5 Gbps per lane
  • Low-Power mode: 10 Mbps asynchronous
  • HS/LP/ULPS mode monitoring
  • Programmable HS delay tuning (0–390 ps)
  • VIH/VIL tuning for LP receiver thresholds
  • LPDLY tuning for LP signal glitch suppression
  • ECC and CRC error detection
  • 12/24-bit DVP pixel output interface
  • Power down and ULPS control per lane
  • APB interface for configuration and control

Block Diagram


        

 
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